1. Field of the Invention
The present invention generally relates to electric clock circuits, and more particularly to a clock circuit that uses a phase-lock loop (PLL) circuit having a phase/frequency detector with reduced jitter at high frequencies.
2. Description of the Related Art
Electric circuits that provide clock signals are used in a wide assortment of electronic devices, and particularly in computer systems. Microprocessors and other computer components, such as random access memory (RAM), use clock signals to synchronize various high-speed operations. These computer clock circuits often use a phase-lock loop (PLL) circuit to de-skew (synchronize) an internal logic control clock to an external system clock.
A typical prior art PLL circuit includes a phase and frequency detector, a low-pass filter, and a voltage-controlled oscillator (VCO). The phase/frequency detector compares two input signals, a reference signal (from the external system clock) and a feedback signal, and generates a phase error signal that is a measure of their phase difference. The phase error signal from the detector is filtered by the low-pass filter and fed into the control input of the VCO. The VCO generates a periodic signal with a frequency which is controlled by the filtered phase error signal. The VCO output is coupled to the feedback input of the phase/frequency detector, thereby forming a feedback loop. If the frequency of the feedback signal is not equal to the frequency of the reference signal, the filtered phase error signal causes the VCO frequency to shift toward the frequency of the reference signal, until the VCO finally locks onto the frequency of the reference. The output of the VCO is then used as the synchronized (internal logic control) signal. The feedback loop may contain other components such as charge pumps, dividers, clock buffers or clock distribution networks. In cases where the incoming data is a self-clocking bit stream, the comparator system is used to extract the clock information from the data stream itself.
FIG. 1 illustrates a sequential phase/frequency detector (PFD) that is commonly used in PLLs. That PFD consists of four flip-flops and a four-input (reset) NAND gate, and has two outputs, up (U) and down (D). Each of these outputs can be in either a low voltage state or a high voltage state, and each has a duty ratio (d.sub.U and d.sub.D) which is the fractional amount of time that a given terminal is in the low state. The phase error signal used by the VCO is a function of these duty ratios (d.sub.U -d.sub.D). This particular PFD has several advantages, among them, aperiodicity and an active phase range of .+-.360.degree. (twice as large of many other PFDs), as noted in "Phaselock Techniques," F. Gardner, pp. 123-125 (1979).
Another conventional sequential phase/frequency detector is described in the article "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE Journal of Solid-State Circuits, vol. 27, no. 1 (November 1992). That circuit is noted as being able to operate at very high frequencies (up to 400 MHz), since its critical path is limited by just three gate delays: two from cross-coupled, two-input NAND gates (in one of the two flip-flops), flops), band one from a four-input reset NAND gate. This PLL uses complementary metal-oxide semiconducting (CMOS) technology.
One problem with phase/frequency detectors is that jitter is introduced into the loop due to the "dead zone." The phase error signal that controls the VCO has a first polarity in the case where the reference signal has a phase lag, and the other polarity when a phase lead is detected. For very small phase differences (e.g., the zero-phase-error, steady-state condition of the locked PLL), in the transition from one polarity to the other there is often a region referred to as the dead zone where the phase error signal is insensitive to phase-difference changes. However, it is important that the control characteristic of the PLL be linear in a phase-difference interval that contains the zero-phase-error point, in order to avoid the VCO uncontrollably changing its phase. In this dead zone (or dead band) the VCO's eventual output signal is unpredictable and liable to dither. Several techniques have accordingly been devised to shrink the range of the dead zone.
One of these techniques is described in U.S. Pat. No. 5,546,052 which is very similar to the circuit of FIG. 1 except for the use of an additional NAND gate (reference numeral 110 of that patent). The reset path delay is increased to reduce the dead zone. The assertion time for all the outputs is extended, which ideally appears as a common-mode signal to the subsequent stages. Unavoidable layout and technology-dependent mismatches in the charge pump and large-area filter stages of the PLL significantly increase the error using such an approach, since the effect is not truly common-mode. Furthermore, the pulse width is extended by four gate delays using this approach (the interval over which the mismatch is integrated), greatly magnifying the error. This approach is generally thus not suitable for very high performance PLLs. See also U.S. Pat. No. 5,491,439.
Another of these techniques is described in U.S. Pat. No. 5,422,603. The dead-zone contribution of the charge pump filter is reduced by using a fully symmetric charge pump architecture, and by fully differential implementation of the loop filter. While this construction is an improvement over the above-noted patents, the pulse width is still determined by the reset path delay and is only coarsely adjustable. A similar design is disclosed in U.S. Pat. No. 5,436,596, in which the reset signal which keeps both the current sink and current source temporarily alive to avoid a dead zone region. A three-input AND gate driven by a signal divided down from the reference clock. The reference clock signal is added to reduce the effects of process, temperature and design features, but that invention also suffers from the same problems as the '603 invention.
In U.S. Pat. No. 4,804,928, a phase/frequency detector is disclosed which is configurable as either a phase or frequency detector. That circuit has the same rest path and delay dependence mentioned above. Unbalanced delays on the charge and discharge paths (reference numerals 16 and 18 of FIG. 1 of that patent) further aggravate the common-mode issues.
A generic phase detector with overlapping UP and DOWN outputs is included as part of the invention of U.S. Pat. No. 5,485,125. An asynchronous reset is available on this phase detector, and is asserted when overlapping outputs are detected, lowering the dead zone. The speed of the reset path (reference numerals 31 and 53 of FIG. 2 of that patent) limits the effectiveness of this approach, as in the other patents.
Yet another approach to minimizing jitter involves minimizing noise input to the VCO via the control voltage lines. See, e.g., U.S. Pat. No. 5,465,075. A plurality of power-down transistors are arranged in the control circuit, and the VCO circuit's gain may be selected at the minimum gain required to lock the PLL over a predetermined range of process and operating conditions. This approach does not address, however, reduction of the dead zone, and the foregoing issues still apply.
Another phase/frequency detector which is reminiscent of FIG. 1 is shown in U.S. Pat. No. 4,739,278, except that the NAND gates have been replaced with NOR gates. The reset gate is coupled to the latches such that additional gate delays are provided to ensure that the output signals of the discriminator reach the full logic amplitudes. The advantage of this adaptation is that the path dependence is reduced from the four-input NAND version of FIG. 1. The limitations of this approach regarding the dead zone are otherwise identical to the detector of FIG. 1.
Many of the foregoing approach to minimizing the dead zone are particularly complicated, and do not completely eliminate dead zone concerns. This is particularly true for high frequencies (greater than 1 GHz) since the dead zone problem becomes more pronounced due to circuit switching speed and rise time limitations (the circuits do not respond unless their switching thresholds have been exceeded). It would, therefore, be desirable and advantageous to devise a PLL clocking circuit having a phase/frequency detector which effectively eliminates jitters resulting from the dead zone at such high frequencies.